The present invention relates to a data processing system having different kinds of processing units and, more particularly, to a data processing system in which one of these processing units is selectively activated.
In recent years, various kinds of microprocessors of relatively cheap prices have been put on the market. For example, many types of intelligent equipment such as word processor systems, communication apparatuses, and the like use a general purpose microprocessor as a major unit for data processing. For the manufacturers of such intelligent equipment, programming of the general purpose microprocessor, namely, development of the software, is the work that is almost as important as design of the peripheral hardware of this general purpose microprocessor.
In development of the software of the intelligent equipment, the developer first makes a source program corresponding to a desired sequence, for example, a word processing sequence. The source program, in this case, is ordinarily written in a language such as, assembly language or a high level language which is easy for the developer to understand. After making the source program, the developer makes an object program using a software development tool or system having an assembler or compiler. The source program is converted by the assembler or compiler to the object program consisting of binary code which can be executed by the special microprocessor. This object program is preliminarily stored into, for example, a ROM, disk memory, or the like prior to being executed by the intelligent equipment.
Hitherto, a data processing system having one microprocessor has been used as the aforementioned software development tool. In the case where a single software development tool is used for development of software for various kinds of intelligent equipment, this development tool needs dedicated assembler or compiler programs corresponding to each of different kinds of microprocessors. Due to this requirement, the software development tool having one microprocessor has the following two drawbacks.
The first drawback is that the object program made cannot be easily debugged in many cases. Namely, when the microprocessor of this development tool is of the same type as the microprocessor to be used in the intelligent equipment, the microprocessor of the development tool can execute and test the object program for the purpose of debugging. However, in the case where the kind of microprocessor of the development tool differs from that of the intelligent equipment, the microprocessor of the development tool cannot be used to debug the object program unless an emulation is executed. This is because the binary code of the object program is recognized as another instruction different from the inherent instruction by the microprocessor of the development tool. In the emulation, the processor of the development tool recognizes the binary code of the object program as data instead of as an execution instruction and virtually executes the object program. However, for this emulation, a plurality of emulation programs must be prepared in accordance with the kinds of microprocessors to be emulated.
The second drawback is that it takes a fairly long time and a high cost to make cross assembler or cross compiler programs corresponding to each of the microprocessors for which software is to be developed. These assembler programs and compiler programs can be executed by the microprocessor of the development tool but produce binary code which can be executed by the microprocessor for which the software is being developed. Generally, the persons who put microprocessors on the market provide reasonably priced self assemblers which produce binary code which can be executed by the microprocessor on which the self assembler is being executed. However, it is the rare case where the suppliers also provide a cross assembler for allowing object programs for their microprocessor to be made by a microprocessor of a different type. It is obvious that a plurality of cross assemblers must be prepared in addition to up to one self assembler in order to allow one microprocessor in the software development tool to make the object programs for various kinds of microprocessors. The number of cross assemblers increases in proportion to the number of kinds of microprocessors for which the software development tool must produce object code. Particularly, in recent situation such that a number of microprocessors of the latest model are developed, there is a large risk such that the time and costs are in vain due to production of cross assemblers.
In addition, although there is not directly concerned with the software development, Japanese Patent Unexamined Publication No. 129673/1983 discloses a data processing system having different kinds of microprocessors. According to this data processing system, the execution programs of the first and second microprocessor units are stored into a single memory unit. This memory unit is connected to the first and second microprocessor units through an address bus and a data bus. Each microprocessor unit selects one of memory locations in the memory unit through the address bus and receives the content at the memory location selected, namely, the processing instruction through the data bus. This data processing system further has an instruction interpreting section, a flip-flop, and a selecting circuit. The instruction interpreting section is connected to the memory unit through the data bus. When change instructions of the first and second microprocessor units are read out from the memory unit, the instruction interpreting section generates an output data to designate either one of the first and second microprocessors in accordance with this instruction. The flip-flop receives the output data from the instruction interpreting section and holds it. The selecting circuit is connected to the flip-flop and activates one of the first and second microprocessor units and also inactivates the other in accordance with the data held in the flip-flop.
However, the instruction interpreting section of this data processing system cannot help increasing in scale since its structure is remarkably complicated due to the following reasons. In other words, the function of the instruction interpreting section itself is equivalent to one microprocessor. The first reason is that the data bus transfers not only the execution instructions of the first and second microprocessor units but also the processing data. Therefore, the instruction interpreting section must discriminate whether the binary code on the data bus is the instruction or the data. The second reason is that the instruction interpreting section must preliminarily know which one of the first and second microprocessor units is active. Otherwise, the instruction interpreting section cannot distinguish whether the processing instruction on the data bus is the processing instruction for the first microprocessor unit or for the second microprocessor unit. In addition to this, there is the case where the processing instruction is constituted by the number of bits larger than the width of the data bus. In this case, the processing instruction is divided into a plurality of words and stored into the memory unit and each word is read out sequentially from the memory unit at a different time. Therefore, to detect the change instructions of the first and second microprocessor units with certainty, the instruction interpreting section must know for each processing instruction, the number of words which will be transferred through the data bus. The third reason is that the change instruction must be the binary code for the non-execution (No op) instruction for the active microprocessor. With the structure having the first and second microprocessor units, the binary code to switch from the first microprocessor unit to the second microprocessor unit and the binary code to switch from the second microprocessor unit to the first microprocessor unit are needed. Namely, the binary codes which can be used as the change instructions are limited. Therefore, the instruction interpreting section must inevitably discriminate the binary code of two or more bytes as the change instruction.
On the other hand, in the case where a DMA (direct memory access) is provided in this data processing system, data is transferred through the data bus between the memory unit and the I/O devices irrespective of the first and second microprocessor units. This causes the structure of the instruction interpreting section to be further complicated.